1. Field of the Invention
This invention relates generally to computing devices utilizing memory devices and to methods and apparatus for managing signals between memory devices and other devices.
2. Description of the Related Art
Many current computing devices include one or more processors and memory devices that engage in high speed bi-directional communication. Data signals, clock signals and error detection signals represent a few of the types of signals transmitted between these devices. For example, a typical dynamic random access memory (DRAM) device may receive data signals and clock signals from a processor by way of a data bus channel and a clock channel, respectively. Although a processor may include logic that provides synchronous clocking for the data bus channel and the clock channel, some conventional DRAMS tend to introduce skew between the signals received from a processor on the data bus channel and the clock channel. The skew is seldom constant, but instead exhibits phase jitter and/or drift over time and as a function of temperature. If the amount of phase jitter exceeds certain thresholds for a given system, the signal received at the memory device will be flagged as an error, resulting in a so-called “memory operating frequency hole.” Memory operating frequency holes can lead to lower device performance or other errors.
One conventional technique to address the issue of phase jitter is to impose sufficient wide band isolation, through silicon design, package design or both, between the processor and the memory device input/outputs (I/Os). This technique tends to be costly. Other conventional techniques involve over or under clocking the processor and/or the memory, which may not be practical for various reasons.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.